`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company: Wuhan University 
// Engineer: Yu Zihao 
// 
// Create Date: 2021/08/1 18:26:53
// Design Name: 
// Module Name: MUX_8
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module MUX_8(
    input wire [7:0] sel,
    input wire [15:0] R0,
    input wire [15:0] R1,
    input wire [15:0] R2,
    input wire [15:0] R3,
    input wire [15:0] R4,
    input wire [15:0] R5,
    input wire [15:0] R6,
    input wire [15:0] R7,
    output reg [15:0] data_out
);
    always@(*)begin
        case(sel)
            8'b00000001 : data_out=R0;
            8'b00000010 : data_out=R1;
            8'b00000100 : data_out=R2;
            8'b00001000 : data_out=R3;
            8'b00010000 : data_out=R4;
            8'b00100000 : data_out=R5;
            8'b01000000 : data_out=R6;
            8'b10000000 : data_out=R7;
            default: data_out=16'b0000000000000000;
        endcase
    end
endmodule
